Short Course on Phase-Locked Loops

On September 16^th 2009, San Diego Chapter of the Circuits and Systems Society will host a Short Course on Phase-Locked Loops given by Professor Michael Perrott.

ABSTRACT

Short Course on Phase-Locked Loops IEEE Circuit and System Society, San Diego, CA, Michael H. Perrott Phase-locked loop (PLL) circuits are a key component of most modern communication circuits, and are also used in a variety of digital processor applications in order to generate high frequency, low jitter clock sources. This tutorial-level presentation will present an overview of analog and digital frequency synthesizers, including basic concepts and recent innovation. Classical analog integer-N synthesizers will first be examined in order to provide background on basic PLL components, modeling, and system level tradeoffs. Analog fractional-N synthesizers will then be presented along with key concepts in Sigma-Delta modulation. Finally, digital frequency synthesizers will be examined with high performance time-to-digital conversion being a particular focus point. High level design and simulation techniques are presented, as well as examples corresponding to recent implementations.

Date & Time:

Wednesday, September 16th, 2009
9:00 am to 12:00 pm
12:00 pm to 1:00 pm - Break
1:00 pm to 2:00 pm

Cost:

Free

RSVP:

Not necessary

Location:

Bldg Q, Qualcomm
6455 Lusk Blvd, San Diego, CA 92121